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| 0 OPB 16450 UART DS433 August 18, 2004 0 0 Product Specification LogiCORETM Facts Core Specifics Introduction This document provides the specification for the OPB Universal Asynchronous Receiver/Transmitter (UART) Intellectual Property (IP). The UART described in this document has been designed incorporating the features described in National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995), (http://www.national.com/pf/PC/PC16550D.html). The National Semiconductor PC16550D data sheet is referenced throughout this document and should be used as the authoritative specification. Differences between the National Semiconductor implementation and the OPB UART Point Design implementation are highlighted and explained in Specification Exceptions Supported Device Family Virtex-II ProTM, VirtexTM, Virtex-IITM, Virtex-4TM, QProTM-R Virtex-II, QPro Virtex-II, Virtex-E, Spartan-IITM, Spartan-IIETM, Spartan-3TM opb_uart16450 Resources Used Version of Core v1.00c Min Slices LUTs 341 357 347 0 Provided with Core Max 341 357 347 0 Features * * Hardware and software register compatible with all standard 16450 UARTs Implements all standard serial interface protocols * * 5, 6, 7, or 8 bits per character Odd, Even, or no parity detection and generation 1, 1.5, or 2 stop bit detection and generation Internal baud rate generator and separate receiver clock input Modem control functions False start bit detection and recovery Prioritized transmit, receive, line status, and modem control interrupts Line break detection and generation Internal loop back diagnostic functionality Receiver Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register Interrupt Identification Register (Read Only) Line Control and Line Status Registers Modem Control and Modem Status Registers FFs Block RAMs Documentation Design File Formats Constraints File Verification Instantiation Template Reference Designs Product Specification. VHDL N/A N/A N/A None Design Tool Requirements Registers Xilinx Implementation Tools Verification Simulation Synthesis Support 5.1i or later N/A ModelSim SE/EE 5.6e or later XST Scratch Register Support provided by Xilinx, Inc. Divisor Latch (least and more significant byte) (c) 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 1 OPB 16450 UART * System clock frequency of 100 MHz UART Background The OPB 16450 performs parallel to serial conversion on characters received from the CPU and serial to parallel conversion on characters received from a modem or microprocessor peripheral. The OPB 16450 is capable of transmitting and receiving 8, 7, 6, or 5 bit characters, with 2, 1.5 or 1 stop bits and odd, even or no parity. The OPB 16450 can transmit and receive independently. The device can be configured and it's status monitored via the internal register set. The OPB 16450 is capable of signaling receiver, transmitter and modem control interrupts. These interrupts can be masked, are prioritized and can be identified by reading an internal register. 16450 UART Design Parameters To allow you to obtain an OPB UART that is uniquely tailored for your system, certain features can be parameterized in the OPB UART design. This allows you to have a design that only utilizes the resources required by your system and runs at the best possible performance. The features that can be parameterized in the Xilinx OPB UART design are shown in Table 1. Table 1: Design Parameters Grouping / Number OPB Interface G1 Feature / Description OPB UART Base Address Parameter Name C_BASEADDR Allowable Values Valid Word Aligned Address. C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR C_BASEADDR +1. Default Value A0000000 VHDL Type std_logic_vector G2 G3 G4 G5 G6 OPB Data Bus Width OPB Address Bus Width Device Block ID(1) C_OPB_DWIDTH C_OPB_AWIDTH C_DEV_BLK_ID 32 32 0-255 0,1. 32 32 0 0 integer integer integer integer std_logic_vector Module Identification C_DEV_MIR_ENABLE Register (1) OPB UART High Address C_HIGHADDR C_HIGHADDR A0001FFF -C_BASEADDR must be a power of 2 >= to C_BASEADDR+1FF F 0 0 1 UART Features G7 G8 G9 External XIN External RCLK Select UART C_HAS_EXTERNAL_X 0,1 IN C_HAS_EXTERNAL_ RCLK C_IS_A_16550 0,1 0,1 integer integer integer 2 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Allowable Parameter Combinations There are no restrictions on parameter combinations. UART I/O Signals The I/O signals for the UART are listed in Table 2. The interfaces referenced in this table are shown in Figure 1 in the UART block diagram. Table 2: UART I/O Signals Initial diagra m State Grouping OPB Slave Signals P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 Signal Name OPB_ABus(0:C_OPB_AWIDT H-1) Interface IPIF I/O I I I I I I O O O O O O Description OPB Address Bus OPB Byte Enable OPB Data Bus Read Not Write OPB Select OPB sequential address (unused) OPB_BE(0:(C_OPB_AWIDTH/ IPIF 8)-1) OPB_DBus(0:C_OPB_DWIDT H-1) OPB_RNW OPB_Select OPB_seqAddr IPIF IPIF IPIF IPIF Sln_DBus(0:C_OPB_DWIDTH IPIF -1) Sln_ErrAck Sln_Retry Sln_ToutSup Sln_XferAck IP2INTC_Irpt IPIF IPIF IPIF IPIF IPIF 0 0 0 0 0 0 Output Data Bus Slave Error Acknowledge (always inactive) Slave Bus Cycle Retry (always inactive) Slave Time Out Suppress (always inactive) Slave Transfer Acknowledge IPIF interrupt Output DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 3 OPB 16450 UART Table 2: UART I/O Signals (Continued) Initial diagra m State 1 Grouping UART Signals P13 P14 rclk Signal Name baudoutN Interface Serial Serial I/O O I Description Transmitter Clock Receiver 16x Clock (Optional. May be driven by baudoutN under control of the C_HAS_EXTERNAL_RCLK parameter). Serial Data Input P15 P16 P17 sin sout xin Serial Serial Serial I O I 1 Serial Data Output Baud Rate Generator reference clock. (Optional. May be driven by OPB_Clk under control of the C_HAS_EXTERNAL_XIN parameter). P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 System P30 P31 P32 xout ctsN dcdN dsrN dtrN riN rtsN ddis out1N out2N rxrdyN txrdyN OPB_Clk OPB_Rst Freeze Serial Modem Modem Modem Modem Modem Modem User User User User User System System System O I I I O I O O O O O O I I I ~XIN Inverted XIN ClearToSend (active low) Data Carrier Detect (active low) Data Set Ready (active low) 1 Data Terminal Ready (active low) Ring Indicator (active low) Request To Send (active low) Driver Disable. Low when CPU is reading OPB UART User controlled output User controlled output DMA control signal DMA control signal System clock System Reset (active high) Freezes UART for software debug (active high) 1 1 1 1 1 1 Parameter - Port Dependencies The width of many of the OPB UART signals depends on parameter. In addition, when certain features are parameterized away, the related input signals are unconnected. The dependencies between the OPB UART design parameters and I/O signals are shown in Table 3. parameters and I/O signals are shown in the following table. 4 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Table 3: Parameter-Port Dependencies Name Design Paramet ers G1 G2 G3 G4 G5 G6 G7 G8 G9 I/O Signals P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 OPB_seqAddr Sln_DBus(0:C_OPB_DWIDTH-1) Sln_ErrAck Sln_Retry Sln_ToutSup Sln_XferAck G2 Width varies with the size of the OPB Data bus. C_BASEADDR C_OPB_DWIDTH C_OPB_AWIDTH C_DEV_BLK_ID C_DEV_MIR_ENABLE D_HIGHADDR C_HAS_EXTERNAL_XIN C_HAS_EXTERNAL_RCLK C_IS_A_16550 OPB_ABus(0:C_OPB_AWIDTH-1) OPB_BE(0:(C_OPB_AWIDTH/8)-1) OPB_DBus(0:C_OPB_DWIDTH-1) OPB_RNW G3 G3 G2 Width varies with the size of the OPB Address bus. Width varies with the size of the OPB Address bus. Width varies with the size of the OPB Data bus. P17 P14 G3 Bus width affects maximum allowable address. Connects XIN to OPB_CLK Connects RCLK to baudoutN P3, P7 P1, P2 Affects Depends G3 Relationship Description Bus width affects maximum allowable address. Affects number of bits in bus. Affects number of bits in bus. DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 5 OPB 16450 UART Table 3: Parameter-Port Dependencies (Continued) Name I/O Signals P12 P13 P14 IP2INTC_Irpt(1) baudoutN rclkK G8, P13 This input is unconnected and UART receiver clock is connected to BAUDOUTn if C_HAS_EXTERNAL_RCLK=0. Affects Depends Relationship Description UART Interrupt Signal P15 P16 P17 sin sout xin G7, P30 This input is unconnected and UART reference clock is connected to OPB_Clk if C_HAS_EXTERNAL_XIN=0. P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 System P30 P31 P32 xout ctsN dcdN dsrN dtrN riN rtsN ddis out1N out2Nn rxrdyN txrdyN OPB_Clk OPB_Rst Freeze UART Register Definition UART Interface (IPIF) The OPB memory map location of the OPB 16450 UART is determined by setting the parameter C_BASEADDR, in the IPIF interface module. The internal registers of the OPB 16450 UART are offset from the C_BASEADDR base address. Additionally, some of the internal registers are accessible only when bit 7of the Line Control Register (LCR) is set. The UART internal register set is described in Table 4. . 6 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Table 4: UART Registers Register Name Receiver Buffer Register (RBR) Transmitter Holding Register (THR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) Line Control Register (LCR) Modem Control Register (MCR) Line Status Register (LSR) Modem Status Register (MSR) Scratch Register (SCR) Divisor Register (DLL) Divisor Register (DLM) Notes: 1. X denotes a don't care LCR(7)1+ C_BASEADDR + Address 0 + C_BASEADDR + 0x1000 0 + C_BASEADDR + 0x1000 0 + C_BASEADDR + 0x1004 0 + C_BASEADDR + 0x1008 X + C_BASEADDR + 0x100C X + C_BASEADDR + 0x1010 X + C_BASEADDR + 0x1014 X + C_BASEADDR + 0x1018 X + C_BASEADDR + 0x101C 1 + C_BASEADDR + 0x1000 1 + C_BASEADDR + 0x1004 Access Read Write Read/Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write UART Register Logic This section tabulates the internal UART registers, including their reset values (if any). Please refer to the National Semiconductor PC16550D UART with FIFOs data sheet (http://www.national.com/pf/PC/PC16550D.html) for a more detailed description of the register behavior. (June, 1995), Receiver Buffer Register As shown in Table 5, the Receiver Buffer Register contains the last received character. Table 5: Receiver Buffer Register Bit Definitions Bit Location 7-0 Name RBR Access Read Reset Value "00000000" Description RBR. Last received character Transmitter Buffer Register As shown in Table 6, the Transmitter Holding Register contains the character to be transmitted next. Table 6: Transmitter Holding Register Bit Definitions Bit Location 7-0 Name THR Access Write Reset Value "11111111" Description THR. Holds the character to be transmitted next Interrupt Enable Register As shown in Table 7, the Interrupt Enable Register contains the bits which enable interrupts. DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 7 OPB 16450 UART Table 7: Interrupt Enable Register Bit Definitions(1) Bit Location 7-4 3 EDSSI Name Access Read/Write Read/Write Reset Value "0" "0" Enable Modem Status Interrupt. "0" -> Disables Modem Status Interrupts. "1" -> Enables Modem Status Interrupts. 2 ELSI Read/Write "0" Enable Receiver Line Status Interrupt. "0" -> Disables Receiver Line Status Interrupts. "1" -> Enables Receiver Line Status Interrupts. 1 ETBEI Read/Write "0" Enable Transmitter Holding Register Empty Interrupt. "0" -> Disables Transmitter Holding Register Empty Interrupts. "1" -> Enables Transmitter Holding Register Interrupts. 0 ERBFI Read/Write "0" Enable Received Data Available Interrupt. "0" -> Disables Received Data Available Interrupts. "1" -> Enables Received Data Available Interrupts. Notes: 1. Bold faced bits are permanently low. Writing to these bits is allowed. Reading always returns "0" Description Interrupt Identification Register As shown in Table 8, the Interrupt Identification Register contains the priority interrupt identification. Table 8: Interrupt Identification Register Bit Definitions(1) Bit Location 7-4 3-1 INTID2 Name Access Read Read Reset Value "0000" "000" Interrupt ID. (2) "011" -> Receiver Line Status (Highest). "010" -> Received Data Available (Second). "110" -> Character Timeout (Second). "001" -> Transmitter Holding Register Empty (Third). "000" -> Modem Status (Fourth). 0 INTPEND Read "1" Interrupt Pending. Interrupt is pending when cleared. Notes: 1. Bold faced bits are permanently low. Reading these bits always return "0" 2. If bit 0 is cleared. See National Semiconductor PC16550D data sheet for more detail. Description Always returns "0000" 8 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Line Control Register As shown in Table 9, the Line Control Register contains the serial communication configuration bits. Table 9: Line Control Register Bit Definitions Bit Location 7 Name DLAB Access Read/Write Reset Value "0" Description Divisor Latch Access Bit. "1" -> Allows access to the Divisor Latch Registers and reading of the FIFO Control Register. 6 5 4 Set Break Stick Parity EPS Read/Write Read/Write Read/Write "0" "0" "0" Set Break. "1" -> Sets SOUT to "0". Stick Parity. "1" -> Forces parity to "1" or "0" based on bits 3 and 4. Even Parity Select. 1 -> Selects Even parity. 0-> Selects Odd parity. 3 2 PEN STB Read/Write Read/Write "0" "0" Parity Enable. "1" -> Enables parity. Number of Stop Bits. "0" -> 1 Stop bit. "1" -> 2 Stop bits or 1.5 if 5 bits/character selected). 1-0 WLS Read/Write "00" Word Length Select. "00" -> 5 bits/character. "01" -> 6 bits/character. "10" -> 7 bits/character. "11" -> 8 bits/character. Modem Control Register As shown in Table 10, the Modem Control Register contains the modem signaling configuration bits. Table 10: Modem Control Register Bit Definitions (1) Bit Location 7-5 4 3 Loop Out2 Name Access Read/Write Read/Write Read/Write Reset Value "000" "0" "0" Loop Back. "1" -> Enables loop back. User Output 2. "1" -> Drives OUT2N low. "0" -> Drives OUT2N high. Description DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 9 OPB 16450 UART Table 10: Modem Control Register Bit Definitions (1) Bit Location 2 Name Out1 Access Read/Write Reset Value "0" User Output 1. "1" -> Drives OUT1N low. "0" -> Drives OUT1N high. 1 RTS Read/Write "0" Request To Send. "1" -> Drives RTSN low. "0" -> Drives RTSN high. 0 DTR Read/Write "0" Data Terminal Ready. "1" -> Drives DTRN low. "0" -> Drives DTRN high. Notes: 1. Bold faced bits permanently low. Description Line Status Register As shown in Table 11, the Line Status Register contains the current status of the receiver and transmitter. Table 11: Line Status Register Bit Definitions Bit Location 7 6 5 4 3 Name Error in RCVR FIFO TEMT THRE BI FE Access Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value "0" "0" "1" "1" "0" Description Error in RCVR FIFO. RCVR FIFO contains at least one receiver error. Transmitter Empty. Transmitter Holding Register Empty. Break Interrupt. Set when SIN is held low for an entire character time. Framing Error. Character missing a stop bit. Receiver resynchs with next character, if possible. 2 1 0 PE OE DR Read/Write Read/Write Read/Write "0" "0" "0" Parity Error. Overrun Error. RBR not read before next character is received. Data Ready. Modem Status Register As shown in Table 12, the Modem Status Register contains the current state of the Modem interface. 10 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Table 12: Modem Status Register Bit Definitions (1) Bit Location 7 6 5 4 3 2 1 0 Name DCD RI DSR CTS DDCD TERI DDSR DCTS Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value "X" "X" "X" "X" "0" "0" "0" "0" Description Data Carrier Detect. Complement of DCDN input. Ring Indicator. Complement of RIN input. Data Set Ready. Complement of DSRN input. Clear To Send. Complement of CTSN input. Delta Data Carrier Detect. Change in DCDN since last MSR read. Trailing Edge Ring Indicator. RIN has changed from a low to a high. Delta Data Set Ready. Change in DSRN since last MSR read. Delta Clear To Send. Change in CTSN since last MSR read. Notes: 1. X represents bit driven by external input. Scratch Register As shown in Table 13, the Scratch Register can be used to hold user data. Table 13: Scratch Register Bit Definitions Bit Location 7-0 Name Scratch Access Read/Write Reset Value "00000000" Scratch. Description Divisor (Least Significant Byte) Register As shown in Table 14, the Divisor (Least Significant Byte) Register holds the least significant byte of the baud rate generator counter. Table 14: Divisor (Least Significant Byte) Register Bit Definitions Bit Location 7-0 Name DLL Access Read/Write Reset Value "00000000" Description Divisor Least Significant Byte. DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 11 OPB 16450 UART Divisor (Most Significant Byte) Register As shown in Table 15, the Divisor (Most Significant Byte) Register holds the most significant byte of the baud rate generator counter. Table 15: Divisor (Most Significant Byte) Register Bit Definitions Bit Location 7-0 Name DLM Access Read/Write Reset Value "00000000" Description Divisor Most Significant Byte. UART Block Diagram The top-level block diagram for the UART is shown in Figure 1. RCLK RXRDYN SIN SOUT OPB RBR/FIFO THR/FIFO Receiver Transmitter TXRDYN Decode and Control DDIS LCR LSR IER IIR MCR MSR SCR DLL DLM SRAM IPIF BAUDOUTN XIN Baud Generator XOUT RTSN MODEM LOGIC DTRN OUT1N OUT2N CTSN DSRN DCDN RIN Figure 1: UART Top-level Block Diagram 12 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Raw UART Interface UART without an OPB interface The raw UART interface (the OPB UART without the OPB IPIF) is nearly identical to the interface described in the National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995), (http://www.national.com/pf/PC/PC16550D.html) with the following major differences: * * * * * * * * Sysclock. All bus transactions and UART operations are synchronized to this input clock. Freeze. Asserting this signal disables interrupts and places the UART receiver and transmitter in the marking state. Xin is a clock enable input, rather than a true clock. Rclk is a clock enable input rather than a true clock. Wr/WrN are clock enables. Rd/RdN are clock enables. AdsN is a clock enable. Three state data bus (D) is separated into a read bus (Dout) and a write bus (D). Dout is always driven. Description of the raw interface signals Sysclock. This is the primary UART reference clock. All UART operations and bus transactions are synchronized to this signal. Xin. Xin is the reference for the UART baud rate generator circuit. Xin is a clock enable input. If Xin is tied high, the baud rate reference will be Sysclock. Otherwise, Xin should be a single Sysclock period pulse high, with whatever duty cycle is required by the application. Rclk. This is the 16x reference for the receiver portion of the UART. It is a clock enable and should be a single Sysclock period pulse high, with whatever duty cycle is required by the application. To simplify a system design Rclk may be tied to the inverse of baudoutN. Dout(7:0). UART read bus. Valid data will appear on this bus on the second Sysclock following Rd/RdN being brought active. This bus is always driven. Ddis. This signal goes low on the second Sysclock following Rd/RdN being brought active. D(7:0). UART write bus.Valid data will be sampled during any clock period in which Wr/WrN are active with a valid address and chip select applied. AdsN. Address Strobe. This is a clock enable. Address pins (A2:A0) and Chip Select pins (Cs0, Cs1 and Cs2N) will be sampled when AdsN is low and held when AdsN is high. Wr/WrN. UART write pins. Data on D(7:0) is sampled during any Sysclock period in which Wr or WrN is active. Rd/RdN. UART read pins. Data from the currently addressed register will appear on Dout(7:0) 2 Sysclock cycles following Rd or RdN being asserted. A(2:0). UART address bus. This address bus is a three bit address. The register map is identical to that described in the National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995): (http://www.national.com/pf/PC/PC16550D.html). DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 13 OPB 16450 UART These pins are sampled when AdsN is low and held when AdsN is high. If AdsN is tied low, A(2:0) must be stable while Rd/RdN/Wr/WrN are active. Cs0, Cs1, Cs2N. UART chip selects. These pins are sampled when AdsN is low and held when AdsN is high. If AdsN is tied low, these pins must be stable while Rd/RdN/Wr/WrN are active. All other signals. All other interface signals are as described in the National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995). (http://www.national.com/pf/PC/PC16550D.html). Design Implementation Target Technology The intended target technology is Virtex-II FPGA Device Utilization and Timing OPB_Clk is capable of running at 100 MHz. XIN and RCLK must be less than 1/2 OPB_Clk frequency. Performance Benchmarks Table 16: Performance and Resource Utilization Benchmarks Parameter Values Slices OPB UART 16450 341 Device Resources Slice Flip-Flops N/A LUTs 357 fMAX (MHz) fMAX N/A Specification Exceptions System Clock The asynchronous microprocessor interface of the National Semiconductor PC16550D is synchronized to the system clock input of the UART. Register Addresses All internal registers reside on a 32 bit word boundary not on 8 bit byte boundaries. Reference Documents The following documents contain reference information important to understanding the UART design: * National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995). (http://www.national.com/pf/PC/PC16550D.html) 14 www.xilinx.com 1-800-255-7778 DS433 August 18, 2004 Product Specification OPB 16450 UART Revision History The following table shows the revision history for this document. Date 10/03/01 05/28/02 07/23/02 01/08/03 05/15/03 07/28/03 08/01/03 05/21/04 06/01/04 8/18/04 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.6 Initial Xilinx release. Update for EDK 1.0 Add XCO parameters for System Generator Update for EDK SP3 Change LS and MS register names Update to new template Add generic per CR 175375; remove conditional text table notes per CR 175368 Update narrative in Device Utilization and Timing section per CR 188487 Correct C_HIGHADDR value Updated for Gmm; updated trademarks and supported device family listing. Revision DS433 August 18, 2004 Product Specification www.xilinx.com 1-800-255-7778 15 |
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